The present invention relates generally to the wafer level packaging, and more particularly relates to the formation of high strength solder joints thereon.
There are a number of conventional arrangements for packaging integrated circuits. Many packaging techniques use a leadframe that has been stamped or etched from a metal (typically copper) sheet to provide electrical interconnects to external devices. One relatively recently developed packaging style, which is sometimes referred to as a Micro SMD (Surface Mount Devices) package, as shown in FIG. 1, which is wafer level CSP. In a micro SMD package, the footprint of the package is generally equal to that of the die size, yielding a relatively dense array outline of contacts on the active side of the silicon IC. In fact, these packages have one of the smallest footprints per I/O count.
Typical micro SMD packages contain bump counts ranging from a four (4) (2×2 array outline) bump count to a thirty (30) bump count (5×6 array outline). At these smaller bump counts, the active side of the array are mounted to a Printed Circuit Board (PCB) in a manner similar to a typical Ball Grid Array (BGA) mount, via conventional solder joints. These packages, given their dense array of I/O contacts, are limited to about thirty (30) bumps due to the solder joint fatigue life. In general, the outer I/O contacts of a package, when mounted to a circuit board, are subjected to greater loading stress than those contacts that are central to the package due to greater DNP (Distance from Neutral Point). Such joint stress, for instance, may be experienced during thermo-cycling and/or during a drop testing. Due in part to the geometry and position of these outermost contact posts relative to those contacts centrally located, any central loads are magnified significantly at the perimeter of the package. Accordingly, contact failure at such outermost contact interfaces is more prevalent.
More recently, Micro SMDxt packages have been developed that have significantly larger bump counts than the array of contacts for a standard SMD package (typically up to a 5×6 array, or 30 bump count). These Micro SMDxt packages 25, as shown in FIG. 1, generally range from thirty-six (36) bumps (a 6×6 array outline) to 100 bumps (a 10×10 outline).
To enable solder mounting of these larger array Micro SMDxt packages, each solder joint incorporates a solder ball consisting of a polymeric core with a copper shell followed by an outer solder layer. Applying a single industry standard reflow process, a significantly higher strength joint can be created due to the flexibility of the polymeric core. Hence, a significantly longer fatigue life can be achieved than a conventional solder joint. Typical of such polymeric core solder balls are those commercially available by Sekisui Corporation of Japan.
However, proliferation of this package family beyond 100 bumps (10×10 array outline) is limited by the solder joint fatigue life. While the polymeric core allows a longer fatigue life than convention solder joints, it still reaches its limit in terms of fatigue life and life under drop/impact conditions. For example, FIG. 2 illustrates a magnified cross-section of a conventional solder ball joint 20 of reflowed solder 21 between a polymeric core solder ball 22 and a contact pad 23 for a micro SMDxt package 25. However, due to isothermal aging exposure, thermal cycling and thermal shock, the solder in these solder joints 20 is more adept to failed (fracture 26) in between the solder ball 22 and the contact pad 23 for larger bump packages
Accordingly, it would be beneficial to provide a high strength solder joint capable of securing a high bump micro SMDxt to a circuit board. Given their many advantages, Micro SMDxt packages in general have recently generated a great deal of interest within the semiconductor industry. Although existing techniques for fabricating, packaging and mounting these Micro SMDxt work well, there are continuing efforts to develop even more efficient designs and mounting techniques.